Date:	Tue, May 24, 2011
Time:	14:20
Place:	IRC East Wing Seminar Room

Abstract: Programmable graphic processor units have evolved into highly parallel, multi-threaded, many-core processors with enormous computational capacity and very high memory bandwidth. We discuss the so called Compute Unified Device Architecture (CUDA) as used on NVIDIA hardware. In the second part of the talk, we introduce the non-equispaced fast Fourier trans form, show which part is computationally most involved, and discuss their acceleration by means of a CUDA implementation.